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| ICS9112-18 Zero Delay, Low Skew Buffer Description The ICS9112-18 is a low jitter, low-skew, high performance PLL based zero delay buffer for high speed applications. Based on ICS's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.3 V. The ICS9112-18 includes a bank of four outputs running at 1X, and another four outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs. Compared to competitive CMOS devices, the ICS9112-18 has the lowest jitter of all. ICS manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world. Features * Packaged in 16 pin narrow SOIC * Zero input-output delay * Four 1X outputs plus four half-X outputs * Output to output skew is less than 250 ps * Output clocks up to 160 MHz at 3.3 V * Ability to generate 2X the input * Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V * Spread SmartTM technology works with spread spectrum clock generators * Advanced, low power, sub-micron CMOS process * 3.0 to 5.5 V operating voltage Block Diagram FBIN CLKIN PLL Mux CLKA1 CLKA2 CLKA3 CLKA4 /2 CLKB1 CLKB2 S2, S1 2 CLKB3 Control Logic CLKB4 1 Revision 050400 Printed 11/15/00 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose * CA * 95126 * (408)295-9800tel* www.icst.com MDS 9112-18 F ICS9112-18 Zero Delay, Low Skew Buffer Pin Assignment ICS9112-18 CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBIN CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Feedback Configuration Table Feedback From Bank A Bank B CLKA1:A4 CLKIN 2XCLKIN CLKB1:B4 CLKIN/2 CLKIN 16 pin narrow (150 mil) SOIC Output Clock Mode Select Table S2 0 0 1 1 S1 0 1 0 1 Clocks A1-A4 Tri-state (high impedance) Running Running Running Clocks B1-B4 Tri-state (high impedance) Tri-state (high impedance) Running Running Internal Generation None PLL Buffer Only (no zero delay) PLL PLL Status On On Off On Pin Descriptions Number 1 2, 3, 14, 15 4, 13 5, 12 6, 7, 10, 11 8 9 16 Name CLKIN CLKA1:4 VDD GND CLKB1:4 S2 S1 FBIN Type I O P P O I I I Description CLocK INput. Connect to input clock source. CLocK A bank of four outputs. Power supply. Connect both pins to same voltage (either 3.3V or 5V). Connect to ground. CLocK B bank of four outputs. These are low skew divide by two of bank A. Select input #2. Selects mode for outputs per table above. Select input #1. Selects mode for outputs per table above. FeedBack INput. Determines outputs per Feedback Configuration Table above. Key: I = Input; O = output; P = power supply connection. External Components The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as close to the device as possible. A series termination resistor of 33 may be used close to the pin for each clock output to reduce reflections. 2 Revision 050400 Printed 11/15/00 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose * CA * 95126 * (408)295-9800tel* www.icst.com MDS 9112-18 F ICS9112-18 Zero Delay, Low Skew Buffer Electrical Specifications Parameter Supply voltage, VDD Inputs and Clock Outputs Electrostatic Discharge Ambient Operating Temperature Soldering Temperature Junction temperature Storage temperature Operating Voltage, VDD Input High Voltage, VIH, CLKIN pin only Input Low Voltage, VIL, CLKIN pin only Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD (Note 2) Short Circuit Current Input Capacitance Input Clock Frequency Output Clock Frequency Output Clock Rise Time, CL=30pF Output Clock Fall Time, CL=30pF Output Clock Duty Cycle, VDD=3.3V Device to Device Skew, equally loaded Output to Output Skew, equally loaded Maximum Absolute Jitter Cycle to Cycle Jitter, 30pF loads Notes: Conditions Referenced to GND Referenced to GND MIL-STD-883 Max of 10 seconds -65 3.00 VDD/2+1 2 0.8 IOH=-18 mA IOL=18 mA IOH=-5 mA No Load, S1 = S2 = 1 Each output S2, S1, FBIN FBIN to CLKA1, S1=S2=1 FBIN to CLKA1, S1=S2=1 Minimum -0.5 -0.5 2000 0 Typical Maximum 7 VDD+0.5 70 260 150 150 5.50 Units V V V C C C C V V V V V V V V mA mA pF MHz MHz ns ns % ps ps ps ps ABSOLUTE MAXIMUM RATINGS (note 1) DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise) VDD/2 VDD/2 VDD/2-1 2.4 0.4 VDD-0.4 44 65 7 20 20 160 160 1.5 1.5 60 700 250 500 AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise) 0.8 to 2.0V 2.0 to 0.8V At 1.4V rising edges at VDD/2 rising edges at VDD/2 66.67 MHz outputs 40 50 300 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With CLKIN = 160 MHz, FBIN to CLKA1 Using Spread Spectrum Input Clocks The ICS9112-18 uses ICS' Spread Smart technology, allowing it to accurately track (pass through) any clocks that use spread spectrum techniques. 3 Revision 050400 Printed 11/15/00 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose * CA * 95126 * (408)295-9800tel* www.icst.com MDS 9112-18 F ICS9112-18 Zero Delay, Low Skew Buffer Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) 16 pin SOIC narrow Symbol A A1 E INDEX AREA H B C 1 2 D A1 e C h x 45 D E e H h L Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 A L B Ordering Information Part/Order Number Marking* Shipping packaging ICS9112BM-18 9112BM-18 tubes ICS9112BM-18T 9112BM-18 tape and reel *Also indicated on the top of the package are the initials ICS in a box. Package 16 pin SOIC 16 pin SOIC Temperature 0-70 C 0-70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 4 Revision 050400 Printed 11/15/00 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose * CA * 95126 * (408)295-9800tel* www.icst.com MDS 9112-18 F |
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